Numerical study of 1200V scaled field stop trench insulated gate bipolar transistor

Trench Insulated Gate Bipolar Transistors (TIGBTs) are the foundation of modern, low, medium, and high-power converters and serve as the main component in diverse power electronic applications today such as Motor drives, Induction heating, UPS, Vacuum cleaners etc. latest growth in Trench IGBTs technologies is focused on increasing its power densities and switching frequencies with the target of competing with Wide Band Gap (WBD) power devices. This thesis aims towards studying of 1.2kV scaled Field Stop Trench IGBT using numerical analysis. In this work, 1.2kV FS-TIGBT was modelled, characterised, and scaled employing the scaling principle in the literature. Towards developing and characterizing the Trench IGBT model, a Sentaurus Technology Computer Aided Design (TCAD) that houses a written program specifically meant and designed for semiconductor physics Finite Element Method (FEM) simulation was deployed. Literature review regarding FEM simulations was carried out as well as the physics involved in IGBT operation. Static and dynamic characteristics of the developed Trench IGBT model was evaluated in depth and a comparison was drawn against the scaled device and it was confirmed that the scaled device k=3 have an improved static (I-V) characteristics mainly due to enhanced Injection Enhancement (IE) effect. For the both conventional and scaled devices (k=1 and k=3), the forward on-sate voltage drop Vce(sat) at current rating of 40A are 1.6V for k1 and 1.4V for k3 at 300K. At the same time, the values for the V_(ce(sat)) for the both devices were increased to 1.9V for k1 and 1.6V for k3 at the junction temperature of 400K for the same current rating. For the scaled device k=3, the on – state voltage drop V_(ce(sat)) was lowered by 12.5% at 300K and 16% at 400K respectively. The increase in collector emitter saturation voltage Vce(sat) at high temperature is due to increase in channel resistance. However, it was confirmed in the course of the study that the scaled device k=3 suffers limitation of short circuit capability and during this period, it has been noticed an occurrence of oscillation and overshoot in the gate-emitter voltage threatening the robustness of the device. The limitation in short circuit capability is due to Collector Induce Barrier Lowering (CIBL) effect caused by conductivity modulation in the middle of the mesa region (channel inversion layer) and this led to increase in the channel conductivity and thus result to current un-saturation. In overcoming the limitation of short circuit capability posed by the scaled device, a new scaled device was proposed. The depth of the p+ emitter in the p-base region for the proposed device was slightly increased in order to mitigate the effect of CIBL in the mesa region and ensure current saturation. The optimal depth of the p+ emitter which gave the expected result in terms of current saturation was 0.24um. Thus, the short circuit capability was improved while maintaining same on-state voltage drop and turn-off losses for the proposed and conventional scaled devices.