High Frequency Gate Driver Design for Gallium Nitride Power Devices

Increasing attention has been drawn to Gallium Nitride (GaN) based power devices, since its superior properties in comparison with Silicon counterparts. Gallium Nitride based power devices are very promising in a wide range application, such as battery chargers, point-of-load dc/dc converters, EV OBC and motor drives. GaN based devices exhibit a much lower specific ON resistance (R_(ds_on)) in comparison with Silicon counterparts. This enables a much smaller die size to a certain current capability, and thereby smaller input as well as output capacitances. The higher saturation velocity and lower capacitances allows fast switching transients. As a result, GaN based devices are capable of operating at a switching frequency around 10 times greater compared to current Silicon based MOSFETs. Therefore, Gallium Nitride device is expected as a candidate for next-generation power device in a near future. While, to make use of all advantages that GaN brings, there are numbers of issues need to overcome. For instance, soft switching technique, packing, gate driver, thermal management as well as converter topology.
This thesis is devoted towards the circuit design and associated application by using Gallium Nitride based power semiconductor devices. It will focus on the characterisation of selected GaN devices and related circuit design as well as the experimental verification. An overview of current power devices and its market is studied first, including overview of current power device market and future projection, comprehensive comparison among different trended power devices as well as key challenges faced by GaN-based devices.
This thesis also compares the difference between e-mode GaNFET and cascode GaNFET. Particularly, the insight characteristics of cascode GaNFET, which comprises unique features of cascode structure, switching transient analysis, switching loss mechanism, effect of parasitic elements. Furthermore, the importance of gate driving loop design of cascode GaN-based application has been addressed. Both SPICE-based simulation and experimental work are conducted for evaluation and verification purpose.
A synchronous buck converter is selected to further evaluate the influence of gate drive circuitry from efficiency perspective. A simulation model is implemented in synchronous buck converter to assess the impact of gate driving loop of cascode GaN device in both hard-switching (CCM) and soft-switching (CRM). Moreover, a prototype hardware with proposed gate driving loop design is presented. By applying the soft-switching and proposed gate driving loop design, the cascode GaN-based synchronous buck converter is demonstrated with 99.15% peak efficiency.
Lastly, this work analyses the specific requirement of d-mode device, such as isolated negative power supply and short-circuit protection. Two d-mode devices have been selected for evaluation purpose, namely, 650V SiC JFET and 1.2kV PSJ GaN HFET. Moreover, the PSJ GaN HFET is expected to be constructed in cascode configuration further to realise a novel high-voltage normally-off GaNFET. Therefore, it is necessary to deeply understand the technical challenge raised by d-mode devices. Accordingly, a protection scheme for normally-on device is proposed, which consists of desaturation scheme and negative power supply protection. The proposed scheme is initially implemented in Cadence Orcad for investigation purpose. A hardware prototype is also made to experimentally analyse the superiority of proposed protection scheme in comparison to state-of-the-art counterparts.
In conclusion, this work is concentrated on the evaluation of cascode GaNFETs. Parasitic effect, gate drive circuity and CRM soft-switching technique are addressed to fully making use of the potential of cascode GaN devices. Moreover, an ultra-fast-response protection scheme for d-mode WBG devices is introduced.