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Novel Approaches to Power Efficient GaN and Negative Capacitance Devices

Kumar, Ashwani (2018) Novel Approaches to Power Efficient GaN and Negative Capacitance Devices. PhD thesis, University of Sheffield.

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Abstract

Recent emergence of data-driven and computation hungry algorithms has fuelled the demand for energy and processing power at an unprecedented rate. Semiconductor industry is, therefore, under constant pressure towards developing energy efficient devices. A Shift towards materials with higher figure-of-merit compared to Si, such as GaN for power conversion is one of the options currently being pursued. A minimisation in parasitic and static power losses in GaN can be brought about by realising on-chip CMOS based gate drivers for GaN power devices. At present, p-channel MOSHFETs in GaN show poor performance due to the low mobility and the severe trade-off between |ION| and |Vth|. For the first time, it is shown that despite a poor hole mobility, it is possible to improve the on-current as well as minimise |ION| - |Vth| trade-off, by adopting a combination of techniques: using an AlGaN cap, biased two-dimensional electron gas, and shrinking source-gate and gate-drain access region and channel lengths. As part of this work, a novel vertical p-channel heterojunction tunnel FET (TFET) utilising polarisation induced tunnel junction (PITJ) is also explored, which unlike common TFETs, shows non-ambipolar transfer characteristics and a better electrostatic control over the tunneling region via the gate. Meeting the ever-increasing demand for computation would require continuous scaling of transistor physical dimensions and supply voltage. While a further reduction in physical dimension is expected to come from adopting a vertical integration scheme, scaling in supply voltage would require achieving sub-60 mV/dec of subthreshold swing. The two common approaches to achieve this are TFETs and negative capacitance (NC) FETs, where the NC operation is commonly associated with ferroelectric materials. This work develops a model to explain sub-60 mV/dec, observed in Ta2O5/ZnO thin-film-transistors, which is governed by the motion of oxygen ions inside Ta2O5, leading to NC under dynamic gate bias sweep.

Item Type: Thesis (PhD)
Keywords: Gallium Nitride, Negative Capacitance, p-channel, Tunnel FETs, Power Efficient, Paraelectric, Ferroelectric, Tunneling, Neuromorphic
Academic Units: The University of Sheffield > Faculty of Engineering (Sheffield) > Electronic and Electrical Engineering (Sheffield)
Identification Number/EthosID: uk.bl.ethos.762576
Depositing User: Mr Ashwani Kumar
Date Deposited: 21 Dec 2018 11:54
Last Modified: 25 Sep 2019 20:05
URI: http://etheses.whiterose.ac.uk/id/eprint/22492

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