Evaluation of Thermal Management Solutions for Power Semiconductors

This thesis addresses the thermal management and reliability concerns of power semiconductor devices from die to system level packaging design. Power electronics is a continuously evolving and challenging field. Systems continue to evolve, demanding increasing functionality within decreasing packaging volume, whilst maintaining stringent reliability requirements. This typically means higher volumetric and gravimetric power densities, which require effective thermal management solutions, to maintain junction temperatures of devices below their maximum and to limit thermally induced stress for the packaging medium. A comparison of thermal performance of Silicon and Silicon Carbide power semiconductor devices mounted on Polycrystalline Diamond (PCD) and Aluminum Nitride (AlN) substrates has been carried out. Detailed simulation and experimental analysis techniques show a 74% reduction in junction to case thermal resistance (Rth (j-c)) can be achieved by replacing the AlN insulating layer with PCD substrate. In order to improve the thermal performance and power density of polycrystalline diamond substrates further at the system level, direct liquid cooling technique of Direct Bonded Copper (DBC) substrates were performed. An empirical model was used to analyse the geometric and thermo-hydraulic dependency upon thermal performance of circular micro pins fins. Results show that micro pin fin direct cooling of DBC can reduce the number of thermal layers in the system, and reduce the thermal resistance by 59% when compared to conventional DBC cooling without a base plate. Thermal management and packaging solutions for the wide band gap semiconductors, such as GaN, is also described in detail. Comparisons of face up and flip chip thermal performance of GaN on Sapphire, Silicon and 6H-SiC substrates in a T0-220 package system is presented. Detailed thermal simulation results analysed using ANSYS® show that a flip chip mounted GaN on sapphire substrate can reduce junction to case thermal resistance by 28% when compared against the face up mounted technique.