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Variability-Aware Circuit Performance Optimisation Through Digital Reconfiguration

Burmester Campos, Pedro (2015) Variability-Aware Circuit Performance Optimisation Through Digital Reconfiguration. PhD thesis, University of York.

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This thesis proposes optimisation methods for improving the performance of circuits imple- mented on a custom reconfigurable hardware platform with knowledge of intrinsic variations, through the use of digital reconfiguration. With the continuing trend of transistor shrinking, stochastic variations become first order effects, posing a significant challenge for device reliability. Traditional device models tend to be too conservative, as the margins are greatly increased to account for these variations. Variation-aware optimisation methods are then required to reduce the performance spread caused by these substrate variations. The Programmable Analogue and Digital Array (PAnDA) is a reconfigurable hardware plat- form which combines the traditional architecture of a Field Programmable Gate Array (FPGA) with the concept of configurable transistor widths, and is used in this thesis as a platform on which variability-aware circuits can be implemented. A model of the PAnDA architecture is designed to allow for rapid prototyping of devices, making the study of the effects of intrinsic variability on circuit performance – which re- quires expensive statistical simulations – feasible. This is achieved by means of importing statistically-enhanced transistor performance data from RandomSPICE simulations into a model of the PAnDA architecture implemented in hardware. Digital reconfiguration is then used to explore the hardware resources available for performance optimisation. A bio-inspired optimisation algorithm is used to explore the large solution space more efficiently. Results from test circuits suggest that variation-aware optimisation can provide a significant reduction in the spread of the distribution of performance across various instances of circuits, as well as an increase in performance for each. Even if transistor geometry flexibility is not available, as is the case of traditional architectures, it is still possible to make use of the substrate variations to reduce spread and increase performance by means of function relocation.

Item Type: Thesis (PhD)
Academic Units: The University of York > Electronics (York)
Identification Number/EthosID: uk.bl.ethos.680624
Depositing User: Dr Pedro Burmester Campos
Date Deposited: 29 Feb 2016 11:52
Last Modified: 08 Sep 2016 13:33
URI: http://etheses.whiterose.ac.uk/id/eprint/11988

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