FEASIBILITY STUDY ON IMPLEMENTING THE “BALL COMPUTER”

As processor cores become ever smaller and more power efficient, coupled with the growth of multicore packages, the ratio of data interconnect power to core power is set to invert. While current technologies for on-chip wireless data communication offer an alternative to hard wired buses, the designs of multicore processors and large array machines still rely on conventional power rails to supply the cores.
This thesis will discuss a range of technologies with the potential to enable the wire-free transmission and efficient storage of power within large processor arrays and consider how this could be extended to a 3-dimensional array of self contained computing nodes. This discussion will also include a review of commercially available CPU cores with sufficiently low power consumption and deal with the issue of cooling, taking into consideration the overall system efficiency. There will also be a brief discussion of wireless communication technologies which could be employed to allow high speed data communication between nodes and a review of a small range of power storage technologies which potentially offer high power density and a rapid charge cycle.