A New Era of EDA: A Gen-AI-aided EDA framework for Hardware Development

Rapid progress in artificial intelligence (AI) has reshaped computing practice, creating strong demand for specialised hardware accelerators. Electronic Design Automation (EDA) tools are central to translating design requirements into hardware, especially for compute-intensive AI workloads. Yet conventional EDA flows struggle to integrate emerging AI-driven methods. This limits their ability to support agile and scalable hardware design. At the same time, existing AI accelerators face challenges of flexibility and efficiency, especially in sparse computation, low-precision arithmetic, and evolving neural models.

This thesis addresses these gaps in current workflows and accelerators. It introduces Natural-Level Synthesis (NLS), a new design stage that uses generative AI (Gen-AI) to translate high-level user intent, expressed in natural language or schematic prompts, into register transfer level (RTL) designs. On this basis, the AI-guided System-on-Chip (AI-SoC) framework structures early system partitioning and design exploration. It incorporates domain knowledge and key non-functional constraints such as power, area, and Intellectual Property (IP) block reuse.

The methods are tested on AI benchmarks including convolutional neural networks (CNNs), recurrent neural networks (RNNs), and sparse or quantised models. Two new metrics, Quality of Generated Hardware (QGH) and Required Design Effort (RDE), are proposed to assess design efficiency and integration effort. Results show that NLS reduces hardware resources, for example lowering digital signal processing (DSP) unit usage, while keeping designs correct and practical. It also matches or improves performance in frequency and latency over manual baselines. The AI-SoC framework improves early design choices by linking functional decomposition with power and integration needs. Together, the methods improve adaptability and cut development effort across abstraction levels.

Overall, this thesis demonstrate a stronger AI–EDA synergy and builds a base for future work on intelligent automation, adaptive accelerators, and scalable hardware generation.