Understanding and Controlling Dynamically-Induced Stochastic Domain Wall Behaviours in Magnetic Nanowires

Stochastic pinning of domain walls (DWs) in Permalloy (Py) nanowires is a significant challenge that needs
to be overcome to produce reliable magnetic nanowire-based devices for memory/logic applications. In this
study, stochastic interactions of vortex DWs (VDWs) with intrinsic defects and artificial notch-shaped
defects have been studied with the aim of understanding their complexity and proposing methods to control
them.
VDW pinning/depinning behaviour in double and single notches showed complex behaviour in real
measurements when compared with quasi-static simulations. Systematic study was performed on VDW
interactions with double and single notches with a range of depths and nanowires’ thicknesses. Results
showed that multi-mode stochastic pinning/depinning behaviour occurred for the vast majority of systems.
However, for large single notches in thick nanowires (t=40nm), single-mode depinning-field-distributions
were observed. It was shown that convergence to single depinning-mode was due to the nature of Walkerbreakdown
transformations that preserve the vortex shape of VDWs, and to the specifics of DWs interaction
with notch and edge roughness.
The dependence of stochastic pinning/depinning behaviours on DW injection processes was also studied. It
was found that DWs injected into nanowires using pulses through orthogonal current-line nucleation
exhibited more deterministic pinning/depinning behaviour than those injected from nucleation pads. This
may be attributed to the process by which DWs depin from the nucleation pad junction.
Additionally, it is shown that pinning/depinning stochasticity can be mitigated by passing VDWs through
sharp bends that act as chirality rectifiers. For certain nanowire/notch geometries, this reduces the number
of accessible pinned DW configurations to a single configuration; thus, producing a single-mode depinningfield-
distribution.
Finally, micromagnetic simulations are used to demonstrate feasibility of DW logic architecture where bits
are encoded using VDW chirality. Designs are proposed for NAND, AND, NOR, OR and FAN-OUT gates.
All gates work by manipulating the interaction of VDWs with Y-shaped junctions and/or notches.