Design, Optimisation, and Analysis of Multi-Level SiC Converters

Silicon Carbide (SiC) devices, known for their thermal stability, high efficiency, and excellent high-temperature performance, have become vital in power electronics after decades of development. These devices offer significant potential for higher switching speeds, lower energy losses, and enhanced system performance. Multi-level converters (MLCs) are especially valued for their capability to increase output voltage levels, minimise power losses, reduce harmonic distortion, and decrease voltage stress on switching devices. This thesis explores the design, application, modelling, and analysis of MLC based on SiC power devices.
This thesis firstly focuses on analysing the performance of three-level topologies (NPC, ANPC, T-type) under varying conditions using precise device parameter models. Key factors like voltage stress and power losses are evaluated, with particular attention to the suitability of SiC MOSFETs in high-voltage aviation applications, providing recommendations for topology selection for different applications. It also highlights a fully integrated three-level NPC module optimised for specific applications, focusing on electrical, electromagnetic, and thermal performance. Unlike combined several two-level modules, it minimises parasitic inductance and uses a novel baseplate for better efficiency and thermal management in aerospace. Using an equivalent heat transfer coefficient instead of CFD simulations quickly estimates power device temperatures, reducing computational time and cost. A linear estimation method determines output power under varying airflow rates and assesses scalability. For the three-level NPC topology, a two-port small-signal model is established. S-parameters are measured using a VNA and converted to Z-parameters for parasitic inductance extraction, with validation showing an error of less than 10%. The extracted parameters are applied to DPT simulation and platform testing, confirming their accuracy.