Mapping of Real-time Applications on Network-on-Chip based MPSOCS.

Mapping of real time applications on real time NoC based MPSoCs.

With the recent developments in semiconductor technology it becomes possible to integrate many different processing elements on single chip, this solution is known as a System-on-Chip (SoC). In such systems, the communication between the different components is also an important aspect. On-chip busses or point-to-point communications have been successfully used. However, as the number of elements increases, on-chip busses are not able to scale and quickly become a communication bottleneck. Packet-switched networks on chip (NoC) have been proposed as a solution for on-chip communication of SoC platforms overcoming many of the limitations of on-chip buses. An important design aspect in such a system is the relative placement of tasks on the processing elements of the platform so that some metrics of interest are optimised commonly referred to as the mapping problem. NoC platforms, because of the benefits that they introduce, will eventually be used in commercial embedded and real-time systems. Despite its significance to embedded systems industry and research communities, little research has been done on providing guarantees for hard real-time applications composed of multiple communicating components running over NoC platforms, in such systems both the computation and the communication between the components must complete within certain deadlines for the system to behave correctly. Application mapping has a direct impact on the interference patterns emerging on the platform where separate tasks and the communications between them interfere with each other when contending over shared resources. Even though a significant amount of research has been carried out on the mapping problem usually the aim is to optimise different metrics and reduce cost in terms of energy consumption. This work tries to solve the mapping problem from a real-time systems perspective, in such systems the overall correctness does not only depend on producing the correct output but also on the time required by the system to produce it, this requirement is most commonly expressed with the concept of a deadline which must always bound the response time of a computational task. Schedulability analysis refers to a set of analytical methods that are able to prove a set of tasks can meet their deadlines when sharing resources under a particular scheduling scheme. This work takes advantage of recent advancements on schedulability analysis that can guarantee the timeliness of tasks, as well as their communications, in distributed real-time systems which specifically run on network on chip platforms using wormhole routing, this analysis is used as a ranking function in a genetic algorithm that is able to evolve task mappings which allow all tasks and communication flows to meet their deadlines in all possible scenarios.