Characterisation of charge carrier defects in high-dielectric-metal-gate and thin film transistor devices

Metal oxide semiconductor (MOS) transistors find application either as a switch or amplifier in high and low power electronic devices. In both sectors, devices rely on the availability of a good insulator layer for achieving desirable performance. The traditional CMOS transistors with Silicon (Si) semiconductor and SiO2 gate insulator has reached its limits with regards to supporting the need for faster and smaller devices. In low power CMOS technology high-dielectric (high-k) materials are being used to replace SiO2 insulator to minimise gate leakage current that arises as a result of device scaling. Another emerging field of application of electronic devices is the field of flat panel displays that aims to make use of transparent thin film MOS transistors. Alternate materials to amorphous silicon (a-Si:H) and poly-silicon (poly-Si) are being researched, to fabricate thin film transistors (TFTs), in favour of traditional materials that have limited optical transparency and mobility. Again, these TFTs are surely in need of good insulators to achieve stable operation against threshold voltage shifts. Performance of MOS transistors is highly dependent on the density of defects in the device. Defects in a transistor could be due to the inherent charge traps in the device materials or the traps formed during fabrication. These charge traps can affect the performance of a transistor such as causing shift in threshold voltage and degrading device mobility and also affect the reliability and stability of the device. Hence it becomes necessary to determine the cause, quantity and impact of defects so that better materials and/or better fabrication processes could be devised to obtain efficient devices.

In this work the aim is to investigate the different defects/traps that impact MOS transistors employed in CMOS and transparent TFT technologies and also to study the impact of these defects on device mobility. Electrical current and capacitance measurements are carried out along with analytical modelling to quantify and understand the nature of the defects in the devices. Charge trap generation and distribution due to post-metallisation annealing of HfO2 based MOS transistor is studied. The density of defects in a ZnO based TFT with Ta2O5 gate insulator is also investigated in this study.