A new switching technique for minimisation of DC-link capacitance in switched reluctance machine drives.

In a switched reluctance (SR) drive, the transfer of the de-fluxing energy in stator
windings back to the dc-link results in a large dc-link capacitance. This limits its
applications where weight and size of the drive are restricted. This thesis describes a
control technique for the dc-link capacitance minimisation in an SR drive. The
proposed control technique maintains the constant power transfer between the de supply
and the H-bridge converter. The average dc-link current over a switching period is kept
constant.
When the output of the integrator, i.e., the average dc-link current, reaches a predefined
value proportional to the torque demand, appropriate switching takes place. This is
achieved by integrating the dc-link current in each switching period. This technique is
called dc-link current integration control (DLCIC). The de-fluxing current from the
outgoing phase is not fed back to the dc-link capacitor. Instead, it is transferred to the
incoming phase to prevent a negative dc-link current, which causes a fluctuation in the
capacitor voltage.
Extensive simulation studies of the DLCIC and other techniques reported in literature
have been performed and the simulation results from DLCIC are compared with those
from other techniques such as Hysteresis Current Control (HCC) and Pulse Width
Modulation Current Control (PWMCC). It has been shown that the peak-to-peak
voltages across the dc-link capacitor from DLCIC are the lowest amongst other
techniques.
The operational speed range of the DLCIC is determined and the optimal turn-on and
turn-off angles are proposed. Filter components under the DLCIC operation has been
designed and compared with the filter for HCC. It is shown that the weight of the filter
for DLCIC is far lower than that for HCC. The proposed control technique have been
validated by experiments. The experimental results show that at the dc-link voltage
ripple which results from DLCIC is much lower than that from HCC. This
demonstrates that DLCIC can minimise the dc-link capacitance in an SR machine drive.