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Hardware Architecture for a Bi-directional Protein Processor Associative Memory

Qadir, Omer (2011) Hardware Architecture for a Bi-directional Protein Processor Associative Memory. PhD thesis, University of York.

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The evolution of Artificial Intelligence has passed through many phases over the years, going from rigorous mathematical grounding to more intuitive bio-inspired approaches. However, to date, it has failed to pass the Turing test. A popular school of thought is that stagnation in the 1970s and 1980s was primarily due to insufficient hardware resources. However, if this had been the only reason, recent history should have seen AI advancing in leaps and bounds – something that is conspicuously absent. Despite the abundance of AI algorithms and machine learning techniques, the state of the art still fails to capture the rich analytical properties of biological beings or their robustness. Moreover, recent research in neuroscience points to a radically different approach to cognition, with distributed divergent connections rather than convergent ones. This leads one to question the entire approach that is prevalent in the discipline of AI today, so that a re-evaluation of the basic fabric of computation may be in order. In practice, the traditional solution for solving difficult AI problems has always been to throw more hardware at it. Today, that means more parallel cores. Although there are a few parallel hardware architectures that are novel, most parallel architectures – and especially the successful ones – simply combine Von Neumann style processors to make a multi-processor environment. The drawbacks of the Von Neumann architecture are widely published in literature. Regardless, even though the novel architectures may not implement non-Von-Neumann style cores, computation is still based on arithmetic and logic units (ALU). The aim of this research is to explore the possibility of whether an alternative hardware architecture inspired from the biological world, and entirely different from traditional processing, may be better suited for implementing intelligent behaviour while also exhibiting robustness.

Item Type: Thesis (PhD)
Keywords: Hardware architecture, artificial intelligence, associative memory, bidirectional, heteroassociative, FPGA, verilog
Academic Units: The University of York > Electronics (York)
Identification Number/EthosID: uk.bl.ethos.547371
Depositing User: Mr Omer Qadir
Date Deposited: 11 Jan 2012 14:59
Last Modified: 08 Sep 2016 12:21
URI: http://etheses.whiterose.ac.uk/id/eprint/2005

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