This thesis focusses on the design of a loss optimized, Silicon Carbide (SiC) based, 800V, multi kilowatt three phase inverter prototype for aerospace application, targeted for high temperature ambient conditions. Given the multiple design constraints such as spatial envelope, mass and efficiency optimization, this research addresses multiple topics that influence the objective. It begins with the overall loss modelling of the inverter, analysis of 2 – level inverter architecture (implementing multiple devices in parallel) to optimize efficiency at high temperatures, impact of paralleling multiple SiC MOSFETs on efficiency, etc.
It then proceeds with analytical modelling of SiC MOSFET switching characteristics with the aim to improve the accuracy of estimation as compared to the existing models. Specifically, the impact of drain to source voltage, junction temperature and load parasitic elements on the switching dynamics is modelled to enhance the accuracy. It is ensured that this modelling methodology relies only on the information provided in the datasheet of the device, which eliminates the need for additional tests to improve the accuracy of loss estimation and thereby saves time and cost. The proposed modelling strategy is verified experimentally by building a suitable double pulse test bench setup.
Further, the key aspects of suitable component selection and placement, PCB layout strategies that suits the temperature requirement, total mass and efficiency targets are delved into. The commutation loop parasitic inductance that impacts the turn off voltage overshoot and thereby the choice of gate resistance that directly impacts the overall efficiency of the inverter is optimized. Suitable placement of multilayer copper planes under the DC link capacitors, in the PCB is analyzed using ANSYS Q3D tool to address the same. Also, the choice of placement of paralleled SiC MOSFETs that gives a tradeoff between either minimizing the commutation loop inductance or minimizing the asymmetry in current sharing between paralleled devices is analyzed. Critical elements of high voltage, high power rated PCB design, such as switching node copper placement, isolation of high voltage and low voltage copper areas and the components that form the boundary between them are discussed. Since SiC MOSFET have lower junction capacitances, they can be switched at high speeds to optimize efficiency. This results in high rate of change in voltages, more so when the design is rated for 800V. The design of gate driver circuitry that can carry out the same, while ensuring minimal cross coupling between power and signal areas of the layout is presented. The full scale prototype is validated extensively at multiple DC link voltages from 400V to 800V and at across a wide range of load upto 30 kW. The impact of load and DC link on efficiency is experimentally recorded. Furthermore, the impact of paralleling of SiC MOSFETs on overall converter efficiency and junction temperature are experimentally observed through temperature logging and power analyzer measurements. To further analyze the variation of the inverter’s efficiency with load and DC link, a MATLAB – Simulink based simulation, that takes into account the device’s switching and conduction losses, based on manufacturer datasheet information, is built. The simulation result exhibited a decent match with the experimental results and also helped deep dive into the distribution of semiconductor losses and their variation with operating conditions. Simulation study is further used to compare the SiC MOSFETs with similar figure of merits but with different chip areas. This helped bring out the load ranges where each device choice would result in maximum efficiency. To improve the accuracy of
II
the Simulink based model that estimates the inverter’s efficiency, the switching loss look up tables are replaced with the switching loss estimated using the accurate analytical models developed and discussed in the previous chapters of this thesis. This resulted in improved accuracy of efficiency estimates.
The experimental device current waveforms captured during the exhaustive validation of the full scale prototype, revealed the asymmetric sharing of currents between paralleled SiC MOSFETs. An in – depth analysis of the PCB layout, based on ANSYS Q3D attributed this asymmetry to the difference in source parasitic inductances of the paralleled MOSFETs. To further optimize the design that mitigates this issue significantly, a novel, multilayer copper layout strategy that takes advantage of flux cancellation between copper planes carrying currents in opposite directions is proposed, analyzed in ANSYS Q3D and experimentally validated. The proposed methodology was found to have improved the current sharing both in the dynamic and static regions of the drain current.
