Investigation and Optimization of Novel Stack Structures

This thesis revolves around investigation and optimization of SSIA and will answer the following - Can the performance of SSIA be significantly improved by the use of advanced design techniques, and will this make them more competitive with register file? To answer this, a baseline performance model has been presented – and this was used to measure the enhancement of new SSIA models utilizing custom design approach (such as wider MOSFET v/s multi-finger MOSFET). The custom design has
been one of the major challenges but using the custom implementation (SSIA_B) we have been able to reduce the power by 15% and area by 5% from standard cell implementation. Another custom implementation (SSIA_C) has been able to reduce the propagation delay by 37% at the cost of the higher area. A tool (SSIA Predictor +
DARWIN) that can assist in the component selection of SSIA has been proposed. Using DARWIN the higher cost of the area of SSIA_C has been reduced. SSIA designs have
been compared with the previous implementation by Bailey and Mullane and register files, SSIA is indeed shown to be very competitive with modern register file structures. In the final analysis, it is clearly demonstrated that significant improvements can be delivered by advanced VLSI techniques and that the performance and scalability of SSIA structures compared to register files is greatly improved. The novelty of this research lies in the thorough investigation and optimization of SSIA.