A Syntax Directed Imperative Language Microprocessor for Reduced Power Consumption and Improved Performance

This thesis investigates high-level Instruction Set Architectures (ISAs) and supporting processor architectures. A Syntax Directed Imperative Language Processor (SDLP) and associated ISA have been defined with the ultimate aim of reducing power consumption and improving performance.
The findings of this thesis suggest that there may be a number of benefits of the SDLP over traditional ISAs and architectures. Initial results suggest that the SDLP ISA places less burden on the memory system by reducing the number of instructions executed for a given program. It also appears that the SDLP could reduce the number of interactions with the memory system for data. These results are significant since a large portion of the total power for a system is consumed by the memory system. It is illustrated how the SDLP requires fewer cycle counts for the equivalent throughput of traditional microprocessor architectures. The implication is that further perfor- mance improvements could be obtained with uniprocessors, before considering multiprocessors.
The main contributions of this thesis include:
• The design of a hybrid control flow and data flow architecture with a supporting Instruction Set Architecture;
• Implementation of an assembler and software-based cycle accurate simulator for the SDLP processor;
• Comparisons of the SDLP architecture with traditional CISC and RISC processors;
• It has been shown that high-level ISAs and supporting processor architectures can reduce the burden on the memory system for both instructions and data; and can reduce the cycle
count of programs.