Early Design Space Exploration of Hard Real-Time Embedded Networks-on-Chip

Networks-On-Chip (NoC) is seen as a solution for addressing the limitation of the current bus-based communication in embedded systems. Some of these systems are designed for executing hard real-time services. In such systems, the services have to deliver output within strict timing constraints since the lateness in output delivery could cause severe consequences to human life. Task mapping is a crucial step for integrating an application and a hardware platform during system design. Existing schedulability analyses are available to evaluate the hard real-time performance of task mapping, but exploring the vast number of task mappings at the early design stage can be challenging due to several issues. These issues are caused by the influence of other design parameters on the hard real-time performance produced by task mapping, the existence of conflicting design objectives with the hard real-time system constraints, the restriction of the current hard real-time evaluation functions for searching alternative task mappings and the enormous evaluation of population-based search heuristics in the current task mapping techniques. This thesis proposes several design space exploration techniques to address these issues. The first technique is proposed for addressing the problem of optimising multiple design parameters while keeping all tasks and messages in the system fully schedulable. The second technique addresses the conflicting objectives problem using a multi-objective optimisation approach. The third technique yields a new metric that is useful for improving task mappings with unschedulable tasks and messages. Finally, the last technique is a new mapping algorithm for constructing a feasible task mapping rather than have to evaluate a population of task mappings to achieve the same objective.